`include "C:\Users\lenovo\Desktop\Files\Linear_RISCV\LR_ver_0\src\include\include.vh"
module  wbu(
    input				WB_sel,
    input   [63:0]      Load_data_wbu,    
    input	[63:0]		Rd_wbu_i,
    input               Reg_W_wbu,
    output              RegWrite_i,
    output	[63:0]		Rd_wbu_o
);
    assign Rd_wbu_o = WB_sel?Load_data_wbu:Rd_wbu_i; 
    assign RegWrite_i = Reg_W_wbu;

endmodule